This application claims priority to Korean Application No. 2000-43680, filed Jul. 28, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to methods of forming integrated circuits in general, and more particularly, to methods of planarizing interlevel insulating layers in integrated circuits.
In general, an interlevel insulating layer can be formed on a cell block to insulate an upper electrode of a capacitor from an overlying wiring line. The interlevel insulating layer can have a step difference caused by the height of the capacitor. A surface of the interlevel insulating layer overlying the capacitor can be higher than that of the interlevel insulating layer overlying another portion of the integrated circuit, such as a peripheral circuit region, a core region, or a test element group (TEG) region.
Since a step difference on an interlevel insulating layer may cause a failure in a photolithography process, the interlevel insulating layer may need to be planarized. One approach to planarization of the interlevel insulating layer can involve introducing a reflow process after forming an interlevel insulating layer using borophosphosilicate glass (BPSG). However, as the height of a capacitor increases to provide a desired capacitance, it may become more difficult to suppress a high step difference on an interlevel insulating layer using the reflow process.
Another approach to planarization of an interlevel insulating layer can involve planarization by Chemical Mechanical Polishing (CMP). However, an edge portion of the interlevel insulating layer overlying a capacitor adjacent to a slanting portion of the interlevel insulating layer between the portions having the step difference therebetween may be over polished. This can be due to a large step difference between a first portion of the interlevel insulating layer overlying the capacitor and a second portion of the interlevel insulating layer overlying a peripheral circuit region or a core region and a slanting portion between the first and second portions is large. The over polishing may result in a failure such as the exposure of an upper electrode of a capacitor or loss of a portion of an upper electrode.
Furthermore, when performing the CMP, the interlevel insulating layer may be deposited to a thickness greater than what may be needed for an actual process. This can decrease a step difference of the interlevel insulating layer by increasing the deposited thickness of the interlevel insulating layer on a core region or a peripheral circuit region on which a capacitor is not formed. However, this approach can make the interlevel insulating layer overlying a core region or a peripheral circuit region thicker, which may lead to etching failure or opening failure caused by incomplete etching during a subsequent dry etching process.
Embodiments according to the present invention can provide methods for planarizing insulating layers on regions that have different rates of etching. Pursuant to these embodiments, an insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.
In some embodiments according to the present, the portion of the insulating layer between the first and second adjacent regions is planarized at the first etch rate and the insulating layer on the second region is planarized at the second etch rate that is less than the first etch rate, to provide a fourth step difference between the first and second regions that is less than the first step difference. In some embodiments according to the present, the planarizations are performed substantially simultaneously.
In some embodiments according to the present, the width of the portion of the insulating layer between the first and second adjacent regions is about 20% to 50% of a width of the second region. In some embodiments according to the present, the width of the portion of the insulating layer between the first and second adjacent regions is in a range between about 20 xcexcm and 80 xcexcm.
In some embodiments according to the present, the first region is a scribe region, a peripheral region, or a test element group region on an integrated circuit wafer and the second region is a cell block region of an integrated circuit memory device on the integrated circuit wafer.
In some embodiments according to the present, the width of the portion of the insulating layer between the first and second adjacent regions is in a range between about 2 xcexcm and 5 xcexcm. In some embodiments according to the present, the first region is a core region located between adjacent cell block regions of an integrated circuit memory device on an integrated circuit wafer, and the second region is a cell block region of the integrated circuit memory device.